System Address Map Initialization in x. Architecture Part 1: PCI- Based Systems. This article serves as a clarification about the PCI expansion ROM address mapping, which was not sufficiently covered in my “Malicious PCI Expansion ROM” article published by Infosec Institute last year (http: //resources. Low- level programmers are sometimes puzzled about the mapping of device memory, such as PCI device memory, to the system address map.

This article explains the initialization of the system address map, focusing on the initialization of the PCI chip registers that control PCI device memory address mapping to the system address map. PCI device memory address mapping is only required if the PCI device contains memory, such as a video card, network card with onboard buffer, or network card that supports PCI expansion ROM, etc. Ethical Hacking Training – Resources (Info. Sec)Ethical Hacking Training – Resources (Info.

Sec)X8. 6/x. 64 system address map is complex due to backward compatibility that must be maintained in the bus protocol in x. Bus protocol being utilized in a system dictates the address mapping of the memory of a device—that’s attached to the bus—to the system address map. Therefore, you must understand the address mapping mechanism of the specific bus protocol to understand the system address map initialization. This article focuses on systems based on the PCI bus protocol. PCI bus protocol is a legacy bus protocol by today’s standard. However, it’s very important to understand how it works in the lowest level in terms of software/firmware, because it’s impossible to understand the later bus protocol, the PCI Express (PCIe) without understanding PCI bus protocol. PCIe is virtually the main bus protocol in every x.

Part 2 of this article will focus on PCIe- based systems. Ethical Hacking Training – Resources (Info.

Codename Category Description Named After Year; Acacia: Motherboard: Intel S460AC4 server motherboard. Has four sockets, uses the 460GX chipset, and supports the.

Sec)Ethical Hacking Training – Resources (Info. Sec)Conventions. There are several different usages of the word “memory” in this article.

It can be confusing for those new to the subject. Therefore, this article uses these conventions: The word “main memory” refers to the RAM modules installed on the motherboard. The word “memory controller” refers to part of the chipset or the CPU that controls the RAM modules and accesses to the RAM modules. Flash memory refers to either the chip on the motherboard that stores the BIOS/UEFI or the chip that stores the PCI expansion ROM contents.

The word “memory range” or “memory address range” means the range, i. CPU memory space.

The word “memory space” means the set of memory addresses accessible by the CPU, i. CPU. Memory in this context could mean RAM, ROM or other forms of memory which can be addressed by the CPU.

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• This article serves as a clarification about the PCI expansion ROM address mapping, which was not sufficiently covered in my “Malicious PCI Expansion ROM” article.

The word “PCI expansion ROM” mostly refers to the ROM chip on a PCI device, except when the context contains other specific explanation. The Boot Process at a Glance. This section explains the boot process in sufficient detail to understand the system address map and other bus protocol- related matters that are explained later in this article. You need to have a clear understanding of the boot process before we get into the system address map and bus protocol- related talks.

The boot process in x. BIOS/UEFI) execution. The platform firmware execution happens prior to the operating system (OS) boot, specifically before the “boot loader” loads and executes the OS. Platform firmware execution can be summarized as follows: Start of execution in the CPU (processor) reset vector. In all platforms, the bootstrap processor (BSP) starts execution by fetching the instruction located in an address known as the reset vector. In x. 86/x. 64 this address is 4. GB minus 1. 6- bytes (FFFF.

This address is always located in the BIOS/UEFI flash memory on the motherboard. Adobe Indesign Cs4 Crack Only Pes. CPU operating mode initialization. In this stage, the platform firmware switches the CPU to the platform firmware CPU operating mode; it could be real mode, “voodoo” mode, or flat protected mode, depending on the platform firmware. X8. 6/x. 64 CPU resets in a modified real mode operating mode, i.

FFFF. Therefore, if the platform firmware CPU operating mode is flat protected mode, it must switch the CPU into that mode. Present- day platform firmware doesn’t use “voodoo” mode as extensively as in the past. In fact, most present- day platform firmware has abandoned its use altogether. For example, UEFI implementations use flat protected mode. Preparation for memory initialization. In this stage there are usually three steps carried out by the platform firmware code: CPU microcode update.

In this step the platform firmware loads the CPU microcode update to the CPU. CPU- specific initialization.

In x. 86/x. 64 CPUs since (at least) the Pentium III and AMD Athlon era, part of the code in this stage usually sets up a temporary stack known as cache- as- RAM (CAR), i. CPU cache acts as temporary (writeable) RAM because at this point of execution there is no writable memory—the RAM hasn’t been initialized yet. Complex code in the platform firmware requires the use of a stack.

In old BIOS, there is some sort of assembler macro trick for return address handling because by default the return address from a function call in x. However, this old trick is not needed anymore, because all present- day CPUs support CAR. If you want to know more about CAR, you can consult the BIOS and Kernel Developer Guide (BKDG) for AMD Family 1. Processor. Section 2. CPU L2 cache as general storage on boot.

CAR is required because main memory (RAM) initialization is a complex task and requires the use of complex code as well. The presence of CAR is an invaluable help here.

Aside from CAR setup, certain CPUs need to initialize some of its machine- specific registers (MSRs); the initialization is usually carried out in this step. Chipset initialization. In this step the chipset registers are initialized, particularly the chipset base address register (BAR). We’ll have a look deeper into BAR later. For the time being, it’s sufficient that you know BAR controls how the chip registers and memory (if the device has its own memory) are mapped to the system address map.

In some chipsets, there is a watch dog timer that must be disabled before memory initialization because it could randomly reset the system. In that case, disabling the watch dog timer is carried out in this step.

Main memory (RAM) initialization. In this step, the memory controller initialization happens. In the past, the memory controller was part of the chipset. Today, that’s no longer the case. The memory controller today is integrated into the CPU. The memory controller initialization and RAM initialization happens together as complementary code, because the platform firmware code must figure out the correct parameters supported by both the memory controller and the RAM modules installed on the system and then initialize both of the components into the “correct” setup. Post memory initialization.

Before this step, the platform firmware code is executed from the flash ROM in the motherboard—and if CAR is enabled, the CPU cache acts as the stack. That’s painfully slow compared to “ordinary” code execution in RAM, especially with instructions fetched into the CPU, because the flash ROM is very slow compared to RAM. Therefore, the platform firmware binary usually copies itself to RAM in this step and continues execution there. In the previous step, the main memory (RAM) is initialized. However, there are several more steps required before the main memory (RAM) can be used to execute the platform firmware code: Memory test. This is a test performed to make sure RAM is ready to be used because it’s possible that some parts of the RAM are broken. The detail of how the test is carried out depends on the boot time requirement of the system.